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WM0831, WM0832
Production Data Sept 1996 Rev 2.1
8-Bit ADCs with Serial Interface and Differential or Dual Inputs
Description
WM0831 and WM0832 are 8-bit analogue to digital converters (ADC) with serial I/O interfaces, providing a choice of input configurations in 8-pin SO or DIP packages. WM0831 has a differential input, also configurable as a single ended input. A-D conversion results are serially output on Data Out (DO) under the control of clock and chip select inputs. The device has a separate voltage reference input. WM0832's two input multiplexer is configurable via the Data In (DI) serial input, as two single ended inputs or a single differential input. The voltage reference operates ratiometrically and is internally connected to the VCC pin. Conversion is initiated by bringing and holding chip select low while providing a clock input. With WM0831's fixed input configuration, the conversion result is output at DO on the clock's falling edges in MSB to LSB order. With WM0832's configurable input multiplexer, data is input to DI on the rising edges of the clock to setup the Mux and initiate conversion. Conversion results appear serially at DO on the falling edges of the clock, first in MSB to LSB order, and then repeated in LSB to MSB order. WM0831/2 operate on 5V or 3.3V supply voltages and are available in small outline and DIP packages for commercial (0 to 70oC) and industrial (-40 to 85oC) temperature ranges.
Features
* * * * * * * * * * * Functionally Equivalent to National Semiconductor ADC0831 and ADC0832 WM0831: Differential or single ended input WM0832: Two single ended inputs or a single differential input Ratiometric reference input (fixed for WM0832) Serial I/O interface Input range 0 to Vcc with Vcc Reference 8 pin package, SO or DIP 5V and 3.3V variants Total Unadjusted Error: 1 LSB 8-bit resolution 32 s conversion time at fclock = 250 kHz
Applications
* * * * Embedding with remote sensors Equipment health monitoring Automotive Industrial control
Block Diagrams
WM0831
CS CLK DI
WM0832
Internal CS
VREF
Vcc
Vcc Input Latch
Mux Select Start Conv
Differential Input
IN+ IN-
CLK
CH0 CH1
Comparator
Input MUX
DAC & SAR Logic
GND
WM0831
Output Latch
DO
WM0832
GND
Output Shift Register
Control Logic
DAC & SAR Logic
Control Logic
Comparator
CS
VREF
DO
Production Data data sheets contain final specifications current on publication date. Supply of products conforms to Wolfson Microelectronics standard terms and conditions.
Wolfson Microelectronics
Lutton Court, Bernard Terrace, Edinburgh EH8 9NX, UK
(c) 1996 Wolfson Microelectronics
Tel: +44 (0) 131 667 9386 Fax: +44 (0) 131 667 5176 email: admin@wolfson.co.uk www: http://www.wolfson.co.uk
WM0831, WM0832
Pin Configuration
Top View 8 pin P (DIP) and D (SO) packages
Ordering Information
5V devices DEVICE WM0831CP WM0831CD WM0831IP WM0831ID WM0832CP WM0832CD WM0832IP WM0832ID 3.3V devices DEVICE WM0831LCP WM0831LCD WM0831LIP WM0831LID WM0832LCP WM0832LCD WM0832LIP WM0832LID TEMP. RANGE 0oC to 70oC 0oC to 70oC -40oC to 85oC -40oC to 85oC 0oC to 70oC 0oC to 70oC -40oC to 85oC -40oC to 85oC PACKAGE 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO TEMP. RANGE 0oC to 70oC 0oC to 70oC -40oC to 85oC -40oC to 85oC 0oC to 70oC 0oC to 70oC -40oC to 85oC -40oC to 85oC PACKAGE 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO 8 pin plastic DIP 8 pin plastic SO
WM0831
WM0832
Absolute Maximum Ratings (note 1) Supply Voltage, Vcc (note 2) . . . . . . . . . . . 6.5 V Input voltage range: Digital Inputs . . . . GND - 0.3 V, VCC + 0.3 V Analogue inputs . . . GND - 0.3 V, VCC + 0.3 V Input current, any pin (note 3) . . . . . . 5 mA Total Input current for package . . . . . . 20 mA
Operating temperature range, TA . . . . TMIN to TMAX WM083_C_ (C suffix) . . . . . . . . . 0oC to +70o C WM083_I_ (I suffix) . . . . . . . . . . -40oC to +85o C Storage Temperature . . . . . . . . - 65oC to +150o C Soldering Information: Lead Temperature 1.6 mm (1/16) from case for 10 seconds: D or P package . . . . . . . 260o C
Recommended Operating Conditions (5V)
Supply voltage High level input voltage Low level input voltage Clock frequency Clock duty cycle (see Note 4) Pulse duration CS high Operating free-air temperature SYMBOL VCC VIH VIL fclock Dclk twH(CS) TA TA MIN 4.5 2 10 40 220 0 -40 70 85 NOMINAL 5 MAX 5.5 0.8 600 60 UNIT V V V KHz % ns o C
C suffix I Suffix
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WM0831, WM0832
Electrical Characteristics (5V)
Vcc = 5V, VREF = 5V,fCLK = 250KHz, TA = TMIN to TMAX, tr = tf = 20 ns, unless otherwise stated. PARAMETER Digital Inputs High level output voltage Low level output voltage High level input current Low level input current High level output (source) current Low level output (sink) current High impedance-state output current (DO) Input capacitance Output capacitance Converter and Multiplexer Total unadjusted error Differential Linearity Supply voltage variation error Common mode error Common mode input voltage range Standby input leakage current (note 10) SYMBOL VOH VOL IIH IIL IOH IOL IOZ CI Co VREF = 5 V. (note 7) (note 8) Vs(error) VCC = 4.75 V to 5.25 V Differential mode VICR (note 9) II(stdby) On-channel VI = 5 V at ON ch. Off-channel VI = 0 V at OFF ch. On-channel VI = 0 V at ON ch. Off-channel VI = 5 V at OFF ch. Excluding MUX addressing time TUE TEST CONDITIONS VCC = 4.75 V, IOH = -360 A VCC = 4.75 V, IOH = -10 A VCC = 5.25 V, IOH = 1.6 mA VIH = 5 V VIL = 0 V VOH = 0 V VOL = VCC VO = 5 V VO = 0 V MIN 2.4 4.5 0.005 -0.005 -24 26 0.01 -0.01 0.4 1 -1 TYP MAX UNIT V V V A A mA mA A A pF pF LSB Bits LSB LSB V A A A A clock periods k
-6.5 8
3 -3
5 5 1 8 1/16 1/16 GND-0.05 VCC+0.05 1 -1 -1 1 8 1/4 1/4
Conversion time Reference Inputs Input resistance to reference ladder Total device Supply current WM0831 Supply current WM0832 Timing Parameters Setup time, CS low or WM0832 data valid before clock Hold time, WM0832 data valid after clock Propagation delay time, output data after clock Output disable time, DO after CS
tconv
Ri(REF)
Can only be tested for WM0831 1.3
2.4
5.9
ICC ICC tsu
( note 11) 350
0.6 2.5
1.25 4.7
mA mA ns
th MSB data first. CL = 100 pF LSB data first. CL = 100 pF CL = 10 pF, RL = 10 k CL = 100 pF, RL = 2 k
90 1500 600 250 500 ns ns ns ns
ns
tpd tdis
125
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WM0831, WM0832
Recommended Operating Conditions (3.3V)
Supply voltage High level input voltage Low level input voltage Clock frequency (Vcc = 3.3V) Clock duty cycle (see Note 4) Pulse duration CS high Operating free-air temperature SYMBOL VCC VIH VIL fclock Dclk twH(CS) TA TA MIN 2.7 2 10 40 220 0 -40 NOMINAL 3.3 MAX 3.6 0.8 600 60 70 85 UNIT V V V KHz % ns o C
C suffix I Suffix
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WM0831, WM0832
Electrical Characteristics (3.3V)
Vcc = 3.3V, fCLK = 250KHz, TA = TMIN to TMAX, tr = tf = 20 ns, unless otherwise stated. PARAMETER Digital Inputs High level output voltage Low level output voltage High level input current Low level input current High level output (source) current Low level output (sink) current High impedance-state output current (DO) Input capacitance Output capacitance Converter and Multiplexer Total unadjusted error Differential Linearity Supply voltage variation error Common mode error Common mode input voltage range Standby input leakage current (note 10) SYMBOL VOH VOL IIH IIL IOH IOL IOZ CI Co VREF = 3.3 V. (note 7) (note 8) Vs(error) VCC = 3 V to 3.6 V Differential mode VICR (note 9) II(stdby) On-channel VI =3.3V at ON ch. Off-channel VI =0 V at OFF ch. On-channel VI =0 V at ON ch. Off-channel VI =3.3V at OFF ch. Excluding MUX addressing time TUE TEST CONDITIONS VCC = 3V, IOH = -360 A VCC = 3 V, IOH = -10 A VCC = 3V, IOH = 1.6 mA VIH = 3.6 V VIL = 0 V VOH = 0 V, TA = 25o C VOL = 0V, TA = 25o C VO = 3.3V, TA = 25o C VO = 0 V, TA = 25o C MIN 2.4 2.8 0.005 -0.005 15 16 0.01 -0.01 5 5 0.4 1 -1 TYP MAX UNIT V V V A A mA mA A A pF pF LSB Bits LSB LSB V A A A A clock periods k
6.5 8
3 -3
1 8 1/16 1/16 GND-0.05 VCC+0.05 1 -1 -1 1 8 1/4 1/4
Conversion time Reference Inputs Input resistance to reference ladder Total device Supply current WM0831 Supply current WM0832 Timing Parameters Setup time, CS low or WM0832 data valid before clock Hold time, WM0832 data valid after clock Propagation delay time, output data after clock Output disable time, DO after CS
tconv
Ri(REF)
Can only be tested for WM0831 1.3
2.4
5.9
ICC ICC tsu
( note 11) 350
0.2 1.5
0.75 2.5
mA mA ns
th MSB data first. CL = 100 pF LSB data first. CL = 100 pF CL = 10 pF, RL = 10 k CL = 100 pF, RL = 2 k
90 200 80 80 500 200 125 250 ns ns ns ns
ns
tpd tdis
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WM0831, WM0832
Electrical Characteristics (continued)
Notes: 1. Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating range limits are given under Recommended Operating Conditions. Guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. 2. All voltage values, except differential voltages are with respect to the ground. When the input voltage VIN at any pin exceeds the power supply rails (GND > VIN > VCC) the absolute value of current at that pin should be limited to 5 mA or less. The 20 mA package input current limits the number of pins that can exceed the power supply boundaries with a 5 mA supply current to four. A clock duty cycle range of 40% to 60% ensures correct operation at all clock frequencies. For a clock with a duty cycle outside these limits, the minimum time the clock is high or low must be at least 666 ns, with the maximum time for clock high or low being 60 ms. All typical values are at VCC = 5 V, TA = 25o C for 5V devices and VCC = 3.3V, TA = 25o C. All parameters are measured under open-loop conditions with zero common mode input voltage (unless otherwise stated). 7. Total Unadjusted Error (TUE) is the sum of integral linearity error, zero code error and full scale error over the output code range. 8. A Differential linearity of "n" bits ensures a code width exists to "n" bits. Hence a Differential Linearity of 8 bits for an 8 bit ADC guarantees no missing codes. 9. For VIN (-) greater than or equal to VIN(+) the digital output code will be 00 Hex. Connected to each analogue input are two diodes which will forward conduct for a diode drop outside the supply rails, VCC and GND. If an analogue input voltage does not exceed the supply voltage by more than 50 mV, the output code will be correct. To use an absolute input voltage range of 0 to VCC a minimum VCC - 0.05 V is required for all variations of temperature. Care should be exercised when testing at low VCC levels with a maximum analogue voltage as this can cause the input diode to conduct, especially at high temperature, and cause errors for analogue inputs near full scale. 10. Standby input leakage currents, are currents going in or out of the on or off channels when the ADC is not performing conversion and the clock input is in a high or low steady-state condition. 11. For WM0832 the reference current is included in the supply current as VREF is internally connected to VCC.
3.
4.
5.
6.
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WM0831, WM0832
Test Circuits and Waveforms
Output Disable Time Voltage Waveforms and Test Circuits
Standby Leakage Current Test Circuit
Detailed Timing Diagrams
WM0832 Data Input Timing Data Output Timing
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WM0831, WM0832
Performance Data (typical)
WM0831: Total Unadjusted Error
1 0.75 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 32 64 96 128 160 192 224 256
Error (lsbs)
Code WM0832: Total Unadjusted Error 1 0.75 0.5 Error (lsbs) 0.25 0 -0.25 -0.5 -0.75 -1 0 32 64 96 128 Code
Test conditions: VCC = 5V. VREF = 5V, Temp = 25oC, FCLK = 250KHz
160
192
224
256
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WM0831, WM0832
Functional Timing Diagrams
WM0831 Timing
WM0832 Timing
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WM0831, WM0832
Pin Descriptions
WM0831 Pin Name Type 1 CS Digital 2 3 4 5 6 7 8 IN+ INGND VREF DO CLK VCC Analogue input Analogue input Supply Analogue input Digital input Digital input Supply Function Chip Select (active low) Positive differential input Negative differential input Analogue and digital ground Voltage reference input Data Output Clock input Positive supply voltage WM0832 Pin Name Type 1 CS Digital 2 3 4 5 6 7 8 Function Chip Select (active low) CH0 Analogue input Channel 0 input to multiplexer (MUX) CH1 Analogue input Channel 1 input to multiplexer (MUX) GND Supply Analogue and digital ground DI Digital input Data input DO Digital input Data Output CLK Digital input Clock input VCC/VREF Supply/Analogue I/P Positive supply voltage and voltage(ratiometric) reference input
Device No WM0831 WM0832
Multiplexer / Package Options Number of Analogue Channels Single Ended Differential 1 1 2 1
Number of Package Pins 8 8
Functional Description
Input and Multiplexer Operation and Addressing WM0831 has two inputs IN+ and IN- configured for differential operation, single ended operation is achieved by grounding IN- to an analogue common or GND. WM0832 uses an input multiplexer scheme with two input channels, configurable for single-ended or differential operation. The single ended input uses the GND pin as its analogue ground reference. WM0831/2 uses a successive approximation routine to perform A/D conversion and employs a sample data comparator structure which always performs conversion on a differential voltage. Conversion takes place on the voltage difference between assigned "+" and "-" inputs and the converter expects the "+" input to be the most positive, if the "+" input is more negative than "-" then the converter gives an all zeros output. Assignment of WM0832 inputs is made for a single-ended signal between an "+" input and (analogue) ground (GND), or for a differential input between CH0 and CH1 inputs of either polarity. For WM0832 prior to the start of every conversion the input configuration is assigned during the MUX addressing sequence by serially shifting data into the Data Input (DI) on the second and third rising edges of the clock input. The MUX address selects which analogue inputs are enabled, either single-ended or differential. For differential inputs the polarity of the inputs are also assigned. The MUX addressing table gives full details of input assignments. Because WM0831 has only one differential input of fixed polarity it does not require addressing. WM0832 MUX Addressing MUX Address SGL/DIF ODD/EVEN Differential MUX Mode 0 0 0 1 Single Ended MUX Mode 1 0 1 1 Channel Number 0 1 + + + +
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WM0831, WM0832
Functional Description (continued)
Initiating Conversion and the Digital Interface WM0831 and WM0832 are controlled from a processor via a Chip Select (CS) input and a serial interface comprising Data Out (DO) and additionally for WM0832 a Data In (DI) input. For WM0831 conversion is initiated by pulling chip select low and inputting a clock signal. On the clock's first falling edge after CS is brought low, DO output comes out of high impedance mode. On the second and subsequent clock falling edges, to a total of nine, the conversion result is output on DO in MSB to LSB order. WM0831 only provides output data in MSB first order. For WM0832 conversion is also initiated by pulling the chip select (CS) line low and inputting a clock signal but MUX addressing information has also to be input on DI. The start bit and the MUX assignment bits on DI are clocked in on the first three rising edges of the clock input which may be generated by the processor or run continuously. WM0832 uses two MUX assignment bits. When the logic "1" start bit is clocked into the start conversion location of the multiplexer input register the analogue MUX inputs are selected. After 1/2 a clock period delay to allow for the selected MUX output to settle the conversion commences using the successive approximation technique. When conversion begins the A/D conversion result from the output of the SARS comparator appears at the DO output on each falling edge of the clock (see Functional Timing Diagrams). With the successive approximation A/D conversion routine the analogue input is compared with the output of a digital to analogue converter (DAC) for each bit by the SARS comparator and a decision made on whether the analogue input is higher or lower than the DAC output. Successive bits, MSB to LSB, are input to the DAC and remain in its input if the analogue comparison decides the analogue input is higher than the DAC output, if not the bit is removed from the DAC input. There is no sample and hold. The input needs to be stable during Tconv period (see Functional Timing Diagrams). The output from the SARS comparator forms the resulting input to the DAC and the A/D conversion output on DO, and is read by the processor as conversion takes place in MSB to LSB order. After 8 clock periods the conversion is complete. For WM0832 the 8 bits of the conversion are stored in an output shift register, after a conversion has completed and MSB first data has been output WM0832 automatically shifts out LSB first data on the DO output. CS must be held low through an entire conversion, all internal registers are cleared when CS is high. To initiate another conversion CS must make a high to low transition and for WM0832 MUX address assignments input to DI. For WM0832 the DI input and DO output can be tied together and controlled via a bidirectional processor I/O bit line. Reference Input The analogue input voltage range, Vmax to Vmin for differential inputs is defined by the voltage applied to the reference input with respect to GND. WM0832 is fixed in a ratiometric mode with VREF internally tied to Vcc, WM0832 has a separate VREF pin and can be used in either ratiometric applications or those requiring absolute accuracy. A ratiometric reference input, typically the Vcc, is the same supply used to power analogue input circuitry and sensors. In such systems under a given input condition the same code will be output with variations in supply voltage because the same ratio change occurs in both the analogue and reference input to the A/D. When used in applications requiring absolute accuracy a suitable time and temperature stable voltage reference source should be used. The voltage source used to drive the reference input should be capable of driving the 2.4 k typical of the SAR resistor ladder. The maximum input voltage to the reference input is the Vcc supply voltage. The minimum for WM0832 can be at least as low as 1 V to allow for direct conversion of sensor outputs with output voltage ranges less than 5 V.
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WM0831, WM0832
Functional Description (continued)
Analogue Inputs. While sampling the analogue inputs short spikes of current enter a "+" input and flow out of the corresponding "-" input at the clock edges during conversion. This current does not cause errors as it decays rapidly and the internal comparator is strobed at the end of a clock period. Care should be exercised if bypass capacitors are used at the inputs, as an apparent offset error can be caused by the capacitor averaging the input current and developing a voltage across the source resistance. Bypass capacitors should not be used with a source resistance greater than 1k. In considering error sources, input leakage current will also cause a voltage drop across the source resistance and hence high impedance sources should be buffered. In differential mode there is a 1/2 clock period interval between sampling the "+" and the "-" inputs. If there is a change in common mode voltage during this interval an error could notionally result. For a sinusoidal common mode signal the error is given by: VERROR = VPEAK (2fCM) (1/(2fCLK)) Where VPEAK = Peak common mode voltage fCM = Common mode signal frequency fCLK = Clock frequency.
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WM0831, WM0832
Package Descriptions
Plastic Small-Outline Package D - 8 pins shown
4.00 3.80 8
A 5
6.20 5.80
1 1.75 1.35
4 0.50 0.25 0.19 x 45O NOM 0.25
0.51 0.25 0.10 0.33 Pin spacing 1.27 B.S.C. 0O to 8O 1.27 0.40
Dimension 'A' Variations N 8 14 16 Min 4.80 8.55 9.80 Max 5.00 8.75 10.00
Notes: A. Dimensions in millimeters. B. Complies with Jedec standard MS-012. C. This drawing is subject to change without notice. D. Body dimensions do not include mold flash or protrusion. E. Dimension A, mould flash or protrusion shall not exceed 0.15mm. Body width, interlead flash or protrusions shall not exceed 0.25mm.
Rev. 1 November 96
Wolfson Microelectronics
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WM0831, WM0832
Package Descriptions
Dual-In-Line Package
N or P
N
0.325 0.290 0.015 Min.
1
N/2
A 0.070 Max.
0.280 0.240
0.210 Max. 105O 90O 0.014 0.008 0.150 0.115 0.005 Min. Pin spacing 0.100 B.S.C. 0.045 0.030 0.022 0.014 Seating plane
Dimension 'A' Variations N 8 14 16 20 Min 0.355 0.735 0.735 0.940 Max 0.400 0.775 0.775 0.975
Notes: A. Dimensions are in inches B. Falls within JEDEC MS-001( 20 pin package is shorter than MS-001) C. N is the maximum number of terminals D. All end pins are partial width pins as shown, except the 14 pin package which is full width.
Rev. 1 November 96
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